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vishay siliconix dg2001 document number: 71398 s11-1185?rev. c, 13-jun-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 low-voltage single spdt analog switch description the dg2001 is a single-pole/double-throw monolithic cmos analog switch designed for high performance switching of analog signals. combining low power, high speed, low on-resistance and small physical size, the dg2001 is ideal for portable and battery powered applications requiring high performance and efficient use of board space. the dg2001 is built on vishay siliconix?s low voltage ji2 process. the dg2001 has a minimum 2000 v, esd protection, per method 3015.7. an epitaxial layer prevents latchup. break-before- make is guaranteed. the switch conducts equally well in both directions when on, and blocks up to the power supply level when off. features ? halogen-free according to iec 61249-2-21 definition ? low voltage operation (1.8 v to 5.5 v) ? low on-resistance - r on : 3 ? ? fast switching - t on : 20 ns, t off : 10 ns ? low leakage - i com : 0.2 na ? low charge injection - q inj : 5 pc ? low power consumption ? ttl/cmos compatible ? esd protection > 2000 v (method 3015.7) ? tsop-6 package ? compliant to rohs directive 2002/95/ec benefits ? reduced power consumption ? simple logic interface ? high accuracy ? reduce board space applications ? cellular phones ? communication systems ? portable test equipment ? battery operated systems ? sample and hold circuits functional block diagram and pin configuration no (source 1 ) com nc (source 2 ) 1 2 3 6 5 top view in v+ gnd 4 tsop-6 truth table logic nc no 0onoff 1offon ordering information temp range package part number - 40 c to 85 c tsop-6 DG2001DV-T1 DG2001DV-T1-e3
www.vishay.com 2 document number: 71398 s11-1185?rev. c, 13-jun-11 vishay siliconix dg2001 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 7 mw/c above 25 c. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit referenced v+ to gnd - 0.3 to + 6 v in, com, nc, no a - 0.3 to (v+ + 0.3) continuous current (any terminal) 50 ma peak current (pulsed at 1 ms, 10 % duty cycle) 200 esd (mil-std-883b, method 3015.7) > 2000 v storage temperature (d suffix) - 65 to 125 c power dissipation (packages) b tsop-6 c 570 mw specifications (v+ = 2 v) parameter symbol test conditions unless otherwise specified v+ = 2 v, 10 % v in = 0.4 v or 1.6 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc v com full 0 v+ v on-resistance r on v+ = 1.8 v, v com = 1 v, i no , i nc = 10 ma room full 15 17 30 32 ? r on flatness d r on flatness v+ = 1.8 v, v com = 0 v to v+, i no , i nc = 10 ma room 5 switch off leakage current g i no(off) i nc(off) v+ = 2.2 v v no , v nc = 0.5 v/1.5 v, v com = 1.5 v/0.5 v room full - 300 - 3.5 300 3.5 pa na i com(off) room full - 300 - 3.5 300 3.5 pa na channel-on leakage current g i com(on) v+ = 2.2 v, v no , v nc = v com = 0.5 v/1.5 v room full - 350 - 3.5 300 3.5 pa na digital control input high voltage v inh full 1.6 v input low voltage v inl full 0.4 input capacitance c in full 4 pf input current i inl or i inh v in = 0 v or v+ full 1 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 1.5 v, r l = 300 ? , c l = 35 pf room full 30 50 53 ns turn-off time t off room full 15 30 33 break-before-make time t d room 1 15 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 1 10 pc off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 71 db crosstalk d x ta l k room - 70 n o , n c off capacitance d c no(off) c nc(off) v in = 0 v or v+, f = 1 mhz room 17 pf channel-on capacitance d c on room 50 power supply power supply range v+ 1.8 2.20 v power supply current i+ v in = 0 v or v+ 0.01 1 a power consumption p c 2.2 w
document number: 71398 s11-1185?rev. c, 13-jun-11 www.vishay.com 3 vishay siliconix dg2001 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 specifications (v+ = 3 v) parameter symbol test conditions unless otherwise specified v+ = 3 v, 10 % v in = 0.4 v or 2 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance r on v+ = 2.7 v, v com = 1.5 v, i no , i nc = 10 ma room full 5 6 9.2 10.2 ? r on flatness d r on flatness v+ = 2.7 v, v com = 0 v to v+, i no , i nc = 10 ma room 3 switch off leakage current g i no(off) , i nc(off) v+ = 3.3 v v no , v nc = 1 v/3 v, v com = 3 v/1 v room full - 400 - 4.5 400 4.5 pa na i com(off) room full - 400 - 4.5 400 4.5 pa na channel-on leakage current g i com(on) v+ = 3.3 v, v no , v nc = v com = 1 v/3 v room full - 450 - 4.5 400 4.5 pa na digital control input high voltage v inh full 2 v input low voltage v inl full 0.4 input capacitance c in full 4 pf input current i inl or i inh v in = 0 v or v+ full 1 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 2 v, r l = 300 ? , c l = 35 pf room full 24 45 48 ns turn-off time t off room full 12 30 33 break-before-make time t d room 1 13 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 3 10 pc off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 71 db crosstalk d x ta l k room - 70 n o , n c off capacitance d c no(off) , c nc(off) v in = 0 v or v+, f = 1 mhz room 17 pf channel-on capacitance d c on room 50 power supply power supply range v+ 2.7 3.3 v power supply current i+ v in = 0 v or v+ 0.01 1 a power consumption p c 3.3 w
www.vishay.com 4 document number: 71398 s11-1185?rev. c, 13-jun-11 vishay siliconix dg2001 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determined by the operating suffix. b. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guarantee by design, nor s ubjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 5 v leakage testing, not production tested. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (v+ = 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, 10 % v in = 0.8 v or 2.4 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc v com full 0 v+ v on-resistance r on v+ = 4.5 v, v com = 3 v, i no , i nc = 10 ma room full 3 4 7 8 ? r on flatness d r on flatness v+ = 4.5 v, v com = 0 v to v+, i no , i nc = 10 ma room 2 switch off leakage current g i no(off) i nc(off) v+ = 5.5 v v no , v nc = 1 v/4.5 v, v com = 4.5 v/1 v room full - 900 - 5.5 900 5.5 pa na i com(off) room full - 900 - 5.5 900 5.5 pa na channel-on leakage current g i com(on) v+ = 5.5 v, v+ = 5.5 v v no , v nc = v com = 1 v/4.5 v room full - 1000 - 5.5 1000 5.5 pa na digital control input high voltage v inh full 2.4 v input low voltage v inl full 0.8 input capacitance c in full 4 pf input current i inl or i inh v in = 0 v or v+ full 1 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 3 v, r l = 300 ? , c l = 35 pf room full 20 37 40 ns turn-off time t off room full 10 27 30 break-before-make time t d room 1 10 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 7 10 pc off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 71 db crosstalk d x ta l k room - 70 source-off capacitance d c no(off) c nc(off) v in = 0 v or v+, f = 1 mhz room 17 pf channel-on capacitance d c on room 50 power supply power supply range v+ 4.5 5.5 v power supply current i+ v in = 0 v or v+ 0.01 1 a power consumption p c 5.5 w
document number: 71398 s11-1185?rev. c, 13-jun-11 www.vishay.com 5 vishay siliconix dg2001 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) r on vs. v com and supply voltage supply current vs. temperature leakage current vs. temperature 0 1 2 3 4 5 6 7 8 9 012345 v com ? analog voltage (v) v+ = 2 v v+ = 3 v v+ = 5 v r on ? on-resistance ( ? ) - 60 - 40 - 20 0 20 40 60 80 100 temperature (c) i+ ? supply current (na) v+ = 5 v v in = 0 v 0.001 0.01 0.1 1 10 - 60 - 40 - 20 0 20 40 60 80 100 temperature (c) v+ = 5.5 v leakage current (pa) 1 10 100 1000 10 000 i com(off) i on(off) /i nc(off) i com(on) r on vs. analog voltage and temperature supply current vs. input switching frequency leakage vs. analog voltage 3 4 5 6 7 8 9 10 11 12 13 012345 v com ? analog voltage (v) r on ? on-resistance ( ? ) v+ = 2 v 40 c 85 c v+ = 5 v 85 c 25 c - - 40 c 25 c input switching frequency (hz) i+ ? supply current (a) 1 10 100 1 k 10 k 100 k 1 m 10 m 0.1 a 1 a 10 a 100 a 1 ma 10 ma - 500 - 400 - 300 - 200 - 100 0 100 200 012345 v com , v no , v nc , ? analog voltage (v) leakage current (pa) v+ = 5 v i com(off) i on(off) /i nc(off) i com(on)
www.vishay.com 6 document number: 71398 s11-1185?rev. c, 13-jun-11 vishay siliconix dg2001 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) switching time vs. temperature and supply voltage switching threshold vs. supply voltage 0 5 10 15 20 25 30 35 - 60 - 40 - 20 0 20 40 60 80 100 temperature (c) t on v+ = 2 v t on , t off , ? switchint time (ns) t on v+ = 3 v t on v+ = 5 v t off v+ = 2 v t off v+ = 3 v t off v+ = 5 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 01234567 upper threshold v+ ? supply voltage (v) v t ? switching threshold (v) low threshold insertion loss, off -isolation crosstalk vs. frequency charge injection vs. analog voltage -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 v+ = 3 v r l = 50 ? oirr x ta l k 100 k 1 m frequency (hz) loss 10 m 100 m 1 g loss, oirr, x tlak (db) v com ? analog voltage (v) -40 -30 -20 -10 0 10 20 30 40 0123456 v+ = 2 v q ? charge injection (pc) v+ = 3 v v+ = 5 v
document number: 71398 s11-1185?rev. c, 13-jun-11 www.vishay.com 7 vishay siliconix dg2001 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 ? v out gnd v+ 50 % 0 v 0 v logic input switch output t on t off logic "1" = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output v out =v com r l r l +r on + 3 v 0.9 x v out t r < 20 ns t f < 20 ns figure 2. break-before-make interval c l (includes fixture and stray capacitance) nc v no no v nc 0 v 3 v 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd v+ c l 35 pf v o r l 300 ? off on on in ? v out v out q = ? v out x c l c l com r gen v out nc or no 3 v in v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. +
www.vishay.com 8 document number: 71398 s11-1185?rev. c, 13-jun-11 vishay siliconix dg2001 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71398 . figure 4. off-isolation in gnd nc or no 0 v, 2.4 v 10 nf com off isolation = 20 log v nc/ no v com r l analyzer v+ v+ com figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
vishay siliconix package information document number: 71200 18-dec-06 www.vishay.com 1 1 2 3 g au ge pl a ne l 5 4 r r c 0.15 m b a b c 0.0 8 0.17 ref s e a ting pl a ne -c- s e a ting pl a ne a 1 a 2 a -a- d -b- e 1 e l 2 (l 1 ) c 4x 1 4x 1 e e1 1 2 3 6 5 4 c 0.15 m b a b -b- e 1 e e e1 5-lead tsop 6-lead tsop tsop: 5/6?lead jedec part number: mo-193c millimeters inches dim min nom max min nom max a 0.91 - 1.10 0.036 - 0.043 a 1 0.01 - 0.10 0.0004 - 0.004 a 2 0.90 - 1.00 0.035 0.03 8 0.039 b 0.30 0.32 0.45 0.012 0.013 0.01 8 c 0.10 0.15 0.20 0.004 0.006 0.00 8 d 2.95 3.05 3.10 0.116 0.120 0.122 e 2.70 2. 8 5 2.9 8 0.106 0.112 0.117 e 1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.95 b s c 0.0374 b s c e 1 1. 8 0 1.90 2.00 0.071 0.075 0.079 l 0.32 - 0.50 0.012 - 0.020 l 1 0.60 ref 0.024 ref l 2 0.25 b s c 0.010 b s c r 0.10 - - 0.004 - - 0 4 8 0 4 8 1 7 nom 7 nom ecn: c-06593-rev. i, 1 8 -dec-06 dwg: 5540
an823 vishay siliconix document number: 71743 27-feb-04 www.vishay.com 1 mounting little foot tsop-6 power mosfets surface mounted power mosfet packaging has been based on integrated circuit and small signal packages. those packages have been modified to provide the improvements in heat transfer required by power mosfets. le adframe materials and design, molding compounds, and die attach materials have been changed. what has remained the same is the footprint of the packages. the basis of the pad design for surface mounted power mosfet is the basic footprint for the package. for the tsop-6 package outline drawing see http://www.vishay.com/doc?71200 and see http://www.vishay.com/doc?72610 for the minimum pad footprint. in converting the footprint to th e pad set for a power mosfet, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. in the case of the tsop-6 package, the electrical connections are very simple. pins 1, 2, 5, and 6 are the drain of the mosfet and are connected together. for a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. also, heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources when looking at heat spread on the pc board. figure 1 shows the copper spreading recommended footprint for the tsop-6 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copp er overlays the basic pattern on pins 1,2,5, and 6. the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and star t the process of spreading the heat so it can be dissipated into th e ambient air. notice that the planar copper is shaped like a ?t? to move heat away from the drain leads in all directions. this pattern uses all the available area underneath the body for this purpose. figure 1. recommended copper spreading footprint 0.049 1.25 0.010 0.25 0.014 0.35 0.074 1.875 0.122 3.1 0.026 0.65 0.167 4.25 0.049 1.25 since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. reflow soldering vishay siliconix surface-mount packages meet solder reflow reliability requirements. devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, hast, or pressure pot. the solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 2 and 3. ramp-up rate +6 c/second maximum temperature @ 155 15 c 120 seconds maximum temperature above 180 c 70 ? 180 seconds maximum t emperature 240 +5/ ? 0 c time at maximum t emperature 20 ? 40 seconds ramp-down rate +6 c/second maximum figure 2. solder reflow temperature profile
an823 vishay siliconix www.vishay.com 2 document number: 71743 27-feb-04 255 ? 260 c 1 4 c/s (max) 3-6 c/s (max) 10 s (max) reflow zone pre-heating zone 3 c/s (max) 140 ? 170 c maximum peak temperature at 240 c is allowed. figure 3. solder reflow temperature and time durations 60-120 s (min) 217 c 60 s (max) thermal performance a basic measure of a device?s thermal performance is the junction-to-case thermal resistance, r jc , or the junction-to-foot thermal resistance, r jf . this parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. table 1 shows the thermal performance of the tsop-6. table 1. equivalent steady state performance?tsop-6 thermal resistance r jf 30 c/w system and electrical impact of tsop-6 in any design, one must take into account the change in mosfet r ds(on) with temperature (figure 4). 0.6 0.8 1.0 1.2 1.4 1.6 ? 50 ? 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 6.1 a on-resistance vs. junction temperature t j ? junction temperature ( c) figure 4. si3434dv r ds(on) ? on-resiistance (normalized)
application note 826 vishay siliconix www.vishay.com document number: 72610 26 revision: 21-jan-08 application note recommended minimum pads for tsop-6 0.119 (3.023) recommended mi nimum pads dimensions in inches/(mm) 0.099 (2.510) 0.064 (1.626) 0.028 (0.699) 0.039 (1.001) 0.020 (0.508) 0.019 (0.493) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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